1. Field of the Invention
The present invention relates to a duty correction circuit correcting a clock duty ratio, a delay locked loop circuit (DLL circuit), a column A/D converter, a solid-state imaging device and a camera system using the duty correction circuit.
2. Description of the Related Art
Generally, in a logic circuit including a sequential circuit and a combination circuit, the sequential circuit is latch-operated to be synchronized with a clock signal.
A flip flop which is a storage device used for the sequential circuit has minimum values in which the device can be operated in a width of a Hi-period and a width of a Low-period of a clock input waveform respectively.
When the clock duty ratio is shifted from 50%, limitations to high-speed operation may be previously determined in the flip flop in view of the clock width.
The minimum values are determined with respect to the width of the Hi-period and the width of the Low-period respectively not with respect to a clock pulse cycle.
Accordingly, the duty ratio, namely, the ratio of the Hi-level period in a signal cycle of the clock signal is preferably 50% in various applications of the logic circuit.
In JP-A-2008-92091 (Patent Document 1), an integrating-type A/D converter is disclosed, which obtains information of lower bits by a Time-to-Digital Converter (TDC) latching and decoding clock signals having different phases using a normal higher bit counter and a ring oscillator.
The duty ratio of the clock signal is preferably 50% also in the integrating-type A/D converter.
FIG. 1 is a diagram showing a configuration of an A/D converter in a system disclosed in Patent Document 1.
An A/D converter 1 includes a comparator 2, a PLL circuit 3, a TDC (Time-to-Digital Converter which performs latch and decode) 4, a higher counter 5 and a transfer bus 6.
In the example, an integrating-type A/D converter having total resolution of 12-bit obtained by adding 10-bit in the higher counter 5 to 2-bit in the lower TDC 4 is shown by using two clock signals CLKA, CLKB whose phases are different by 90 degrees.
A reference voltage RAMP having a ramp waveform in which a voltage value linearly varies with time is compared to an input voltage VSL in the comparator 2, and a compared result is outputted as a signal VCO.
The higher counter 5 starts or stops operations at a timing when the signal VCO varies, and the lower TDC 4 latches information of the clock signals having different phases.
FIGS. 2A, 2B are diagrams for explaining the principle of the lower TDC which obtains resolution higher than a clock frequency.
When values of two clock signals CLKA, CLKB whose phases are different by 90 degrees are latched at the timing when the signal VCO varies, four types of phase information can be obtained in one cycle of the clock frequency.
Information of lower 2-bits can be obtained by decoding the four types of codes.
As the duty ratio of both clock signals is 50% in FIG. 2A, appearance probability of the four types of codes is equal, however, when the duty ratio of the clock signals deviates as shown in FIG. 2B, appearance probability of codes is biased.
This reduces DNL (differential non linearity) which is one of performance indexes of the A/D converter.
Accordingly, it is desirable that the duty ratio of the clock signal is 50% also in this case.
On the other hand, a duty correction circuit having a first latch circuit and a second latch circuit is proposed in Japanese Patent No. 3753925 (Patent Document 2).
In the first latch circuit, an output of one NAND gate is feedback connected to an input of the other NAND gate in respective NAND gates, and complementary clock signals in whose phase difference is a half cycle are supplied to the other inputs of respective NAND gates.
In the second latch circuit, an output of one NAND gate is feedback connected to an input of the other NAND gate in respective NAND gates, and outputs of the respective NAND gates of the first latch circuit are supplied to the other inputs of the respective NAND gates. A duty correction circuit including NOR gates instead of the NAND gates is also proposed.